1. Field of the Invention
This invention is related to the field of processors and, more particularly, to processing load/store memory operations in processors.
2. Description of the Related Art
Processors generally include support for load memory operations and store memory operations to facilitate transfer of data between the processors and memory to which the processors may be coupled. As used herein, a load memory operation is an operation specifying a transfer of data from a main memory to the processor (although the transfer may be completed in cache). A store memory operation is an operation specifying a transfer of data from the processor to memory. Load and store memory operations may be an implicit part of an instruction which includes a memory operation, or may be explicit instructions, in various implementations. Load and store memory operations are more succinctly referred to herein as loads and stores, respectively.
A given load/store specifies the transfer of one or more bytes beginning at a memory address calculated during execution of the load/store. This memory address is referred to as the data address of the load/store. The load/store itself (or the instruction from which the load/store is derived) is located by an instruction address used to fetch the instruction, also referred to as the program counter address (or PC). The data address is typically calculated by adding one or more address operands specified by the load/store to generate an effective address or virtual address, which may optionally be translated through an address translation mechanism to a physical address of a memory location within the memory.
Many processors execute loads speculatively, and out of program order with respect to other instructions (more briefly “out of order” herein). The program order of operations is the order in which the operations would be executed if they were executed one at a time and non-speculatively. The program order is created by the programmer (and/or compiler) of the program being executed. The loads can execute out of order with respect to previous stores to the same data address (or at least an overlapping addresses, where at least one byte updated by the store is accessed by the load). In such cases, the speculative execution of the load returns incorrect data. When the prior store is subsequently executed, the incorrect speculative execution of the load is detected. The incorrect data must be flushed and the correct data accessed. Performance is reduced in the processor when the corrective actions are needed.